1. Field of the Invention
The present invention relates to a semiconductor chip or die carrier having a reduced size and, more particularly, a semiconductor die carrier affording an external interface having a high-density of electrically conductive contacts concentrated within a very small area and designed to shield the interconnection between the electrical contacts.
2. Description of the Related Art
Semiconductor packages typically contain a semiconductor die having bonding pads formed thereon, a plurality of leads connected to the bonding pads of the semiconductor die, and insulative packaging material formed around the semiconductor die and inner portions of the leads. Such a semiconductor package allows the transmission of electrical signals between the semiconductor die and an interface surface, such as a printed circuit board (PCB), via the bonding pads of the semiconductor die, and electrically conductive pads between the bonding pads and the leads, the leads themselves, and traces on the interface surface.
In the prior art, various methods are known for providing the electrically conductive path between the semiconductor die and the leads of the semiconductor package. Such methods, commonly referred to as bonding techniques, include C4 (controlled collapse die connection) bonding, wire bonding, and TAB (Tape Automated Bonding).
Conventional semiconductor packages suffer from many deficiencies. Conventional PGA (Pin Grid Array) packages, for example, tend to take up large amounts of circuit board area. Indeed, PGA packages generally increase significantly in size as more input/output interconnections are needed, suggesting that future PGA packages for microprocessors will take up even more board area than existing PGA packages.
The manner in which conventional C4 and other bonding technologies are currently being used contributes to the aforementioned area usage problem. For example, in C4 technology, the interconnections provide useful electrical connections, but do not provide an adequate amount of mechanical strength for the types of leads now in use. Moreover, C4 connections are not typically applicable for use within pluggable semiconductor packages. Consequently, in the assembly of PGAs, manufacturers who use conventional C4 bonding technology require that the portions of the leads extending externally from the PGA must be spaced apart to a significant extent. Of course, such spacing increases the area of the PCB that will be occupied by the PGA. Moreover, the use of a multi-layer conductor for supporting the semiconductor die within the PGA package also adds to the size and cost of the PGA package. Furthermore, conventional C4 bonding technology can result in problems with individual lead parasites, inspectability and testing problems, and problems relating to touch-up and repair of the connections.
In addition to increasing the size of conventional PGA-type semiconductor packages, the use of leads that are intentionally spread apart to compensate for mechanical insufficiencies and to allow for pluggable and/or non-pluggable mounting, and the use of multi-layer conductors for supporting the semiconductor die within such packages, all contribute to deficiencies associated with conventional PGA-type semiconductor packages. These deficiencies include a lengthening in the amount of distance that electrical signals must travel within the semiconductor package, which lengthening affects signal propagation times; an increase in the amount of noise imparted to such electrical signals; an elevation in the power requirements for the semiconductor package; and an increase in the complexity of processes required to manufacture the semiconductor package.
Another problem associated with conventional PGA-type semiconductor packages is that such packages, when not used with a socket, are commonly mounted on PCBs using conventional plated-through hole technology. This necessitates the performance of a soldering step, and such mounting technique increases the complexity and expense of the manufacturing operation. Of course, the use of solder strictly limits upgradability of the assembly, thereby making it difficult to replace components.
The cost of the ceramic packaging material and brazed pin assembly is another disadvantage of PGA-type packages. In addition, such packages have low-performance heat sink characteristics, and such packages are costly to manufacture because they include an excessive number of manufacturing processes.
Another problem associated with conventional semiconductor chip carriers relates to electrical interference. As the speed of microprocessors and other electrical components increases, and as the airwaves are filled with all different types of spurious electrical signals coming in from different sources, the requirement for shielded connectors becomes acute. A shielded connector is similar to a coaxial connector wherein a central pin is surrounded by an insulated material, such as Teflon®, and the Teflon® is surrounded by a gold-plated cylindrical member which, in turn, is surrounded by plastic and with interconnecting means being provided for connecting the coaxial connector components. In a semiconductor chip carrier, it is desirable to have both high-density, as well as individual shielding of each contact.
From the foregoing, it can be understood that conventional semiconductor packages, such as PGA-type packages, take up large amounts of board space. In addition, they are frequently not removably pluggable, and are not easily tested in the field or during manufacture. It is common that such conventional semiconductor packages experience greater amounts of noise and have increased power requirements due to the long distances signals must travel within such packages. Usually, in conventional semiconductor packages, the space occupied by the entire package is many times greater than the space actually required for the semiconductor die.
U.S. Pat. No. 6,577,003 which issued to Crane, Jr. et al. on Jun. 10, 2003 discloses a semiconductor chip carrier affording a high-density external interface. The disclosure of U.S. Pat. No. 6,577,003 is incorporated herein by reference. Although high density is achieved in the chip carrier of U.S. Pat. No. 6,577,003, the electrical contacts of said chip carrier are not shielded.
As a result of the foregoing deficiencies incurred in semiconductor packaging technology, the latter is not sufficient to meet the needs of existing and/or future semiconductor and computer technology. Semiconductor packaging technology has already failed to keep pace with semiconductor die technology and, as computer and microprocessor speeds continue to climb, with greater interference surrounding such packages, and with space efficiency becoming increasingly important, semiconductor packages having even smaller area requirements will be required, and such semiconductor packages must be suitably shielded.